Soft-FPGA-Othello

• 日本語はこちら(Japanese version)

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• GitHub Soft-FPGA-Othello
• December 1, 2025 Now, Editing…
• December 1, 2025 Still under creation. It doesn’t work yet.

• November 28, 2025 Forked from Soft-FPGA-TD4.

• Breadboard diagram (planned)

• Plan to implement an Othello game in Verilog, convert it to C++ source using Verilator, and run it on Raspberry Pi Pico2.
• No FPGA required. It runs solely on Pico2.
• Verilog source runs without hardware FPGA! That’s why it’s soft-FPGA.
• soft-FPGA is an abbreviation for Software Defined FPGA. It’s a coined term I created, inspired by Software Defined Radio.

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Development Environment

• November 28, 2025 The development environment is planned to be changed.
• I want to make it buildable and executable using Docker.

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FAQ

Q1: Do I need to modify the C++ source output by Verilator?

• A: No.
  • Details here: FAQ-Q1

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Notes

Verilog Coding Standard

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• GitHub Soft-FPGA-Othello
• Japanese version is here
• Translated by Grok.

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